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searching for CPU cache 24 found (203 total)

alternate case: cPU cache

Intel 82497 (257 words) [view diff] exact match in snippet view article find links to article

the Pentium processor (735\90,815\100, 1000\120, 1110\133) to form a CPU cache chip set designed for high performance servers and function-rich desktops

List of MediaTek systems on chips (2,129 words) [view diff] exact match in snippet view article find links to article

Model number CPU (ISA) Fab CPU CPU cache GPU Memory technology Wireless radio technologies Released MT6205 ARM7 (ARMv5) GSM MT6216 No GPU GSM/GPRS Class

List of UNISOC systems on chips (632 words) [view diff] exact match in snippet view article find links to article

Model number Fab ISA CPU CPU cache GPU Memory technology Wireless radio technologies Released Utilizing devices SC8803G 40 nm LP ARM9 Up to 256 MHz single-core

PrivateCore (610 words) [view diff] exact match in snippet view article find links to article

a secure hypervisor into the CPU cache and acting as a gateway to encrypt memory paging in and out between the CPU cache and RAM. vCage memory encryption

Kernel (operating system) (10,162 words) [view diff] no match in snippet view article

such resources, and optimizes the utilization of common resources e.g. CPU & cache usage, file systems, and network sockets. On most systems, the kernel

Generation of primes (1,138 words) [view diff] exact match in snippet view article find links to article

small sieve segment buffers which are normally sized to fit within the CPU cache; page segmented wheel sieves including special variations of the Sieve

Advanced Synchronization Facility (281 words) [view diff] exact match in snippet view article find links to article

capability to start, end and abort transactional execution and to mark CPU cache lines for protected memory access in transactional code regions. It contains

Netgear WGR614L (270 words) [view diff] exact match in snippet view article find links to article

kB instruction cache 16 kB data cache 1000 byte pre-fetch cache 4 MB CPU cache 2 dBi gain antennas (1 internal and 1 external dipole) 802.11 b/g wireless

Tegra (8,108 words) [view diff] exact match in snippet view article find links to article

troublesome when using online video streaming services. Common features: CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB 40 nm semiconductor technology

Das U-Boot (1,643 words) [view diff] exact match in snippet view article find links to article

do some initial hardware configuration (e.g. DRAM initialization using CPU cache as RAM) and load the larger, fully featured version of U-Boot. Regardless

List of Java keywords (3,054 words) [view diff] exact match in snippet view article find links to article

and not from the CPU cache, and that every write to a volatile variable will be written to main memory, and not just to the CPU cache. Methods, classes

Apple Workgroup Server (201 words) [view diff] exact match in snippet view article find links to article

(DAT) and a PDS card containing a fast SCSI connection and a 256k level 2 CPU cache. Mac OS Supported: System 7.0.1 to Mac OS 8.1 Workgroup Server 60 July

Volunteer computing (1,829 words) [view diff] exact match in snippet view article find links to article

impact performance of the PC. This is due to increased usage of the CPU, CPU cache, local storage, and network connection. If RAM is a limitation, increased

In-memory processing (1,928 words) [view diff] no match in snippet view article find links to article

that is accessed does not need to be forwarded to the CPU or affect the CPU' cache, but is dealt with immediately. Processing-near-Memory (PnM) New 3D arrangements

Trie (3,395 words) [view diff] exact match in snippet view article find links to article

string sorting algorithm as of 2007, accompanied for its efficient use of CPU cache. A special kind of trie, called a suffix tree, can be used to index all

IBM FlashSystem (2,728 words) [view diff] no match in snippet view article find links to article

scaling to 6 units or 1.8 PB usable in a 42U rack. A9000R units share CPU, cache and access paths with their neighbours, leveraging a zero-tuning data

Booting (10,320 words) [view diff] exact match in snippet view article find links to article

initialization using CPU cache as RAM) and load the larger, fully featured version of U-Boot. Some CPUs and SoCs may not use CPU cache as RAM on boot process

Stream processing (4,575 words) [view diff] exact match in snippet view article find links to article

these attributes are not needed this results in wasteful usage of the CPU cache. Additionally, a SIMD instruction will typically expect the data it will

MacBook Pro (Apple silicon) (2,347 words) [view diff] no match in snippet view article

configuration 10-core CPU — 12-core CPU — 12-core CPU 16-core CPU — 16-core CPU — Cache L1 cache High-performance cores: 192 KB L1i, 128 KB L1d Energy-efficient

Web server (9,990 words) [view diff] exact match in snippet view article find links to article

other programming techniques, such as (e.g.): minimization of possible CPU cache misses; minimization of possible CPU branch mispredictions in critical

ZSpace (company) (1,736 words) [view diff] exact match in snippet view article

stylus. The processor is an AMD 7th generation APU that combines the CPU cache and discrete class Radeon GPU on the same chip die. The company's technology

UEFI (9,773 words) [view diff] exact match in snippet view article find links to article

for the specific architecture. It initializes a temporary memory (often CPU cache as RAM, or SoC on-chip SRAM, CAR) and serves as the system's software

CPUID (10,521 words) [view diff] exact match in snippet view article find links to article

state save/restore: XSAVE, XRSTOR, XSETBV, XGETBV instructions 26 27 ss CPU cache implements self-snoop osxsave XSAVE enabled by OS 27 28 htt Max APIC IDs

X86 instruction listings (15,280 words) [view diff] exact match in snippet view article find links to article

to all bytes in a memory region that has the size and alignment of a CPU cache line and contains the byte addressed by DS:rAX. 3 Zen 1 RDPRU Read processor